1. Field of the Invention
The present invention relates to the field of hardware logic circuits and in particular to dynamic hardware logic implemented in computer processors.
2. Description and Disadvantages of Prior Art
In particular high-clocked computer processors are implemented in dynamic logic, which involves a respective cycle-related high switching activity. Such high switching activities of fast dynamic circuits result in 3 to 4 times the power consumption compared to static hardware logic solutions, which are by far slower than dynamic solutions. The high power consumption is due to the clocking and the precharging activities required in dynamic logic. Precharging dynamic logic is a general task for keeping the input lines of any logic function at a properly defined voltage level at the beginning of each cycle independently of the setting of the input lines of said logic function, before the input data enters the circuit. Considering the road map of the CMOS technology, leakage problems—being the reason why precharging is necessary—will follow next as major power consumer besides the regular precharge after the dynamic node has been discharged after valid input signals.
In prior art there are several possibilities to reduce power. One is to turn off the logic and the clocking in case of long-term inactivities. These measures are known under the pseudonyms sleep mode and nap modes. Such measures can be applied for example in laptops or other handheld computing devices, where the idle times are very high. In high-end systems, however, with high utilization this is of no use.
The problems of prior art dynamic logic are further detailed with the example of DOMINO-type dynamic logic as follows and with reference to FIG. 1.
Domino type dynamic logic is a clocked logic. The clock (CLK) controls the precharge phase of a dynamic gate 136 implementing some given logic function. During this phase a dynamic node 134 within the gate is loaded (precharged) to “1”. This is done in every cycle independent of the logic state of the input depicted with variable names H—1, H—2, H—3, I—1, I—2, and L—0 exemplarily in FIG. 1.
During the evaluation phase the dynamic load is either discharged or holds its charged state. Compared to a purely static gate, which doesn't switch at all if the input signal is stable, the dynamic logic consumes power for the clocking itself and the precharge of the dynamic node.
In R. Montoye et. al., “A Double precision Floating Point Multiply”, ISSCC 2003, Vol. 46, pp. 336, Digest of technical papers, Visuals Supplement, pp. 270, so-called digital mid-cycle latches are disclosed connected at the output of such dynamic logic function for saving the states of a respective last evaluation phase of the logic function.
FIG. 1 shows such latch 138 as published in above reference to reduce the switching activities. However, the latch setup time and the stability of the latch are crucial for acceptance in real applications:
First, the set-up time for the latch 138 reduces the speed of the circuit. Second, the latch 138 can only be applied, when the logic function 136 is quite simple, and limited to quite short stacks of transistors connected in series in a path between precharge node and a foot device 112 connected to ground, wherein said transistor stacks must not be larger in number than only two or three stacks switched in parallel. Thus, this prior art approach with such mid-cycle latch is of limited value only.
When, for example, the logic function 136 is more complex, for example has a larger plurality of transistor stacks having a length of 4 transistors including the foot transistor device 112, this prior art approach does not work anymore, as the input to the latch 138 is too instable due to the fact that the precharged node 134 turns ON transistor 111 (T11). Going from precharge to evaluation, the clock turns ON transistor 109 (T9) as well, while the dynamic node 134 still holds the value of “1”. So, transistors 111 (T11) and 109 (T9) are active and pull node 132 to ground. But actually, this should not happen, because the logic function 136 pulls the dynamic node 134 to “0” as well, but with a certain switching delay.
In particular with reference to FIG. 1 only a logic function comprising a stack of 3 transistors T2, T3, T4/T5, and a second stack of two transistors T2, T6, and a third stack of one transistor T7 including a universal foot transistor 112, has been combined with LSDL latches for experimental purposes. Experience shows, however, that the latch 138 is not stable enough and the circuit is error prone. The reason for that instability will be explained as follows for sake of completeness:
Assume that the 11_node 132 is set to “1” and the dynamic node is precharged to “1”. During the precharge phase the switching transistor 111 (T11) is switched ON, and the transistor T9 is turned OFF. Transistor T10 is also OFF, because the latch 138 is set to “1”. When the clk_p at node 130 is pulled to “1”, the evaluation phase starts. Transistor 109 T9 is turned ON immediately. If the logic function in the N-Fet stack is too complex, it takes some time to pull the dynamic node 134 to “0”. Transistor 111 T11 can thus still be switched ON and starts to pull the 11_node 132 to “0”. If that level erroneously is propagated to the output (latch_out), the predecessing dynamic gate—latch 138—changes its state, which is not recoverable and would produce a severe hardware error. Such instability is thus not tolerable.